`timescale 1ns/1ns

// Writes incoming data to stdout
module monitor(
	input		CLK_I,
	input		RST_I,
	input		STB_I,
	input	[31:0]	DAT_I,
	input		WE_I,
	output		ACK_O
);

reg	ack_r;

assign	ACK_O = ack_r;

always @(posedge CLK_I) begin
	if (RST_I) begin
		ack_r <= 1'b0;
	end else begin
		ack_r <= STB_I;
		if (STB_I & WE_I) begin
			$display("%x", DAT_I);
		end
	end
end

endmodule
